A semiconductor integrated circuit device (IC) composed of MOS transistors, etc., requires ESD resistance with respect to surge voltage and surge current impressed upon an external terminal (input/output pad) of the semiconductor integrated circuit device owing to electrostatic discharge. In general, therefore, an electrostatic protection circuit is connected to the external terminal. One such electrostatic protection circuit uses a protection terminal that relies upon a grounded-gate NMOS transistor.
With the progress that has been made in producing more miniscule semiconductor integrated circuit devices in recent years, resistance of the internal transistors to electrostatic discharge is of greater importance. Some examples of such an electrostatic protection circuit are disclosed in Non-Patent Documents 1-2 and Patent Document 1, respectively.
[Non-Patent Document 1] AJITH AMERASEKERA, “ESD in Silicon Integrated Circuits”, Second Edition, WILEY, 2002, p. 117-118
[Non-Patent Document 2] IEEE Reliability Physics Symposium 1987, Page 169 to 173
[Patent Document 1] US2005/0231866A1